Mr. Kapusta is a Principal Process Development Engineer in GE Research's Microelectronics Laboratory, focused on the fabrication processes and system integration of next generation electronics packages and interconnect technologies. He earned his Bachelor of Science Degree in Chemistry at the State University of New York Oswego in 1996.
Since joining GE Research in 1999, his knowledge and contributions have led to the success of many programs involving the integration of advanced semiconductors in such areas as Power Overlay (POL), Chip On Flex (COF), Chip Scale Packaging (CSP), 3-D MCM stacking, Ultra-Thin die stacking, Multi-Chip Modules (MCM’s) and Photonic Integration. As technical lead for external contacts, he has also contributed to the success of many space electronics projects under contract and direction of the Space Vehicles Directorate/VSSE at the Air Force Research Laboratory (AFRL) in addition to several DARPA and DOD contracts. He is a principal contributor and has led programs for MEMS integration, Wafer-level Packaging and Advanced electronic systems for Microwave and Millimeterwave applications for several GE businesses. The past several years of his research has been focused on the Tech Transfer of the POL-kW process to GE Businesses and Strategic Partners. He has over 50 US patents, Author of 50+ publications and he also holds a 6sigma Greenbelt/DFSS Certification.
When not developing advanced packaging technologies, Mr. Kapusta is an avid fisherman that enjoys spending time on Lake Ontario fishing for Salmon and Steelhead, and fly fishing local trout streams.